This application relies from priority upon Korean Patent Application No. 2000-05360, filed on Feb. 3, 2000, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a nonvolatile storage device and, more particularly, to a voltage regulator for nonvolatile storage devices of the electrically erasable and programmable semiconductor type.
Nonvolatile data storage devices, such as flash memory devices, include an array of memory cells for storing the data. Each memory cell is formed of a MOS transistor whose gate electrode, located over its channel region, is a so-called floating gate. This electrode has a high direct current (DC) impedance toward all the other terminals of the same cell, and also towards the circuit in which the cell is connected. The cell further includes a second electrode, called the control gate electrode, which is driven by means of appropriate control voltages for storing (xe2x80x9cwritingxe2x80x9d) data and retrieving (xe2x80x9creadingxe2x80x9d) data. The other electrodes of the transistor are known as its drain, source and bulk (or body) terminals.
The amount of electrical charge present on the floating gate can be changed by applying appropriate voltage values to the cell terminals. The change is using phenomena known as Fowler-Nordheim""s Tunneling and/or Channel Hot Electron Injection. Different amounts of charges result in the transistor being placed in either one of two logic states. The first state (referred to as xe2x80x9can OFF statexe2x80x9d) is of xe2x80x9chighxe2x80x9d threshold voltage (existing in a threshold voltage range of 6V to 7V), and the second state (referred to as xe2x80x9can ON state) is of xe2x80x9clowxe2x80x9d threshold voltage (existing in a threshold voltage range of 1V to 3V).
Since the floating gate has high impedance toward any other terminals of the cell, the stored charge can persist therein for an indefinite length of time, even after the power supply voltage to the circuit, which contains it, has been cut off. The cell has, therefore, characteristics of a nonvolatile memory.
A read operation determines whether the memory cell has the OFF or the ON states. During the read operation of a cell, a specified voltage (e.g., 4.5V) is applied to its control gate and a ground voltage is applied to its source. If the memory cell has the OFF state, no current flows from its drain to its source. This makes a voltage of a bit line increased, so that the memory cell is judged to have the OFF state by a well-known sense amplifier (not shown). If the memory cell has the ON state, current flows from its drain to its source. This makes the voltage of the bit line lowered, and thereby the memory cell is judged to have the ON state by the sense amplifier.
It will be appreciated by the above description that the memory device should have the capability of applying diverse voltages to the cell.
Referring to FIG. 1, there is illustrated a block diagram which shows a NOR-type flash memory device in the prior art that uses a conventional voltage regulator. The memory device of FIG. 1 comprises an array 10 of memory cells arranged as a matrix. The matrix is points at the intersections of rectangularly arranged rows (called the word lines WL0 to WLi), and columns (called bit lines BL0 to BLj).
A voltage VPPi from a word line voltage generating circuit 30 is supplied to a word line WLi through a decoder 20 as a word line voltage (or a read voltage). The word line voltage generating circuit 30 consists of a high voltage generator 32 and a voltage regulator 34.
The high voltage generator 32 generates a high voltage VPP. High voltage VPP is higher than a power supply voltage VCC, when a boost enable signal EN is activated as a control signal. (The high voltage generator 32 also includes a booster circuit well known in the art.) The voltage regulator 34 adjusts the high voltage VPP, so as to produce a word line voltage VPPi of the required level. High voltage VPP is maintained at the power supply voltage level VCC when the boost enable signal EN is inactivated.
Referring now to FIG. 2, a circuit diagram of voltage regulator 34 in the prior art is shown. Voltage regulator 34 consists of a comparator 35, a PMOS transistor MP1 used as a driver, and two resistors R1 and R2 used as a divider, which are connected as illustrated in the figure. The comparator 35 judges whether an output voltage Vdiv of the divider (R1 and R2) is lower than a reference voltage Vref, and the PMOS transistor MP1 operates according to a judgment result of the comparator 35. For example, if, as a judgment result of the voltage regulator 34, the voltage VPPi is lower than a required voltage level (Vref greater than Vdiv), the PMOS transistor MP1 supplies current from the voltage VPP to an output terminal VPPi, so that the output voltage VPPi is increased up to the required voltage level. On the other hand, if the voltage VPPi is higher than the required level (Vref less than Vdiv), the current supply through the PMOS transistor MP1 is blocked, so that the voltage VPPi is lowered down to the required voltage level.
Referring now also to FIG. 3, an operation is described. The output voltage VPP of the high voltage generator 32 is maintained at the power supply voltage level when the boost enable signal EN is at an inactivation state. On the other hand, when the boost enable signal EN is at an activation state (at time t1), the high voltage generator 32 generates the high voltage VPP, which is boosted from the power supply voltage level VCC in short time (e.g., several nanoseconds). The voltage regulator 34 adjusts the high voltage VPP thus generated so as to have the output VPPi of the required voltage level, that is, a word line voltage VWL.
Voltage regulator 34 has a problem, however. Since the voltage VPPi adjusted by the voltage regulator 34 is always sensed, a DC current path is formed between the high voltage VPP and the ground voltage. This causes the capacity of the high voltage to be reduced, since current leaks through the divider. This is partly ameliorated by designing the resistors R1 and R2 to have relatively large values, the DC current between the high voltage VPP and the ground voltage is reduced. This, however, slows down a response speed of the voltage regulator 34. The main cause of the drop of the response speed is RC-type delay, owing both to a capacitance value of the PMOS transistor MP1 having large driving capacity, and a resistance value of the divider R1, R2.
As also illustrated in FIG. 3, to account for the RC type delay, the voltage VPPi adjusted by the voltage regulator 34 is not clamped exactly at a required voltage level VWL. Instead, the voltage VPPi is designed to overshoot, by increasing over the required voltage level. Overshooting is between points of time t2 and t3, as illustrated by dashed circle A in FIG. 3. (The overshot voltage level is determined by the RC delay time).
Unavoidably, the overshot voltage VPPi is applied to a selected word line WLi through the decoder 20 as a word line voltage VWL. As a result, since the word line voltage VWL is higher than a required voltage level, read fail occurs, especially toward a memory cell of an OFF state. This is because the word line voltage VWL exists in a threshold voltage distribution of the OFF state, or because sensing margin for the memory cell of the OFF state is reduced. Therefore, it is preferred to exactly clamp the voltage VPPi at a required voltage level without the overshooting of the voltage VPPi (in FIG. 3, a portion marked by a dotted line A).
The invention overcomes this problem in the prior art.
The invention provides a semiconductor flash memory device that has a voltage generating circuit for supplying through an output terminal a word line voltage clamped exactly at voltage levels as required. Clamping prevents the overshooting problem.
More specifically, the voltage generating circuit includes a high voltage generator for generating a high voltage that is higher than the power supply voltage. The voltage generating circuit also includes a voltage regulator circuit having two voltage regulators, both receiving the high voltage. The first regulator outputs an intermediate voltage that is constantly lower than the high voltage. The second regulator receives the intermediate voltage, and outputs the final word line voltage.
The second regulator is connected to the first regulator without the feedback arrangement of the prior art. Lacking in a feedback arrangement, the circuit of the invention does not waste leakage current.